1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly a semiconductor device which can suppress generation of a leak current as well as a method of manufacturing the same.
2. Description of the Background Art
Semiconductor devices provided with field-effect transistors have been known. FIG. 30 is a schematic cross section showing a semiconductor device in the prior art. Referring to FIG. 30, description will now be given on a conventional semiconductor device.
In FIG. 30, a semiconductor device is provided with field-effect transistors 138a and 138b formed on a semiconductor substrate 101. Further, a p-well 102 and an n-well 103 are formed at semiconductor substrate 101. An isolating oxide film 104 is formed at a main surface of semiconductor substrate 101 for isolating element formation regions from each other. In a region provided with p-well 102, n.sup.- -type impurity diffusion regions 110a and 110b as well as n.sup.+ -type impurity diffusion regions 111a and 111b are formed at the main surface of semiconductor substrate 101. These n.sup.- -type impurity diffusion regions 110a and 110b as well as n.sup.+ -type impurity diffusion regions 111a and 111b form source/drain regions. In a channel region located between n.sup.- -type impurity diffusion regions 110a and 110b, a gate electrode 106a is formed on the main surface of semiconductor substrate 101 with a gate insulating film 105a therebetween. Side walls 107a and 107b made of TEOS oxide films are formed on side surfaces of gate electrode 106a, respectively. High-melting-point metal silicide layers 108a-108c are formed on gate electrode 106a and n.sup.+ -type impurity diffusion regions 111a and 111b. Gate electrode 106a and gate insulating film 105a as well as source/drain regions 110a, 110b, 111a and 111b form field-effect transistor 138a.
In the region provided with n-well 103, p.sup.- -type impurity diffusion regions 112a and 112b as well as p.sup.+ -type impurity diffusion regions 113a and 113b are formed at the main surface of semiconductor substrate 101. These p.sup.- -type impurity diffusion regions 112a and 112b as well as p.sup.+ -type impurity diffusion regions 113a and 113b form the source/drain regions. On a channel region located between p.sup.- -type impurity diffusion regions 112a and 112b, a gate electrode 106b is formed on the main surface of semiconductor substrate 101 with a gate insulating film 105b therebetween. Side walls 107c and 107d made of TEOS oxide films are formed on the side surfaces of gate electrode 106b, respectively. High-melting-point metal silicide layers 108d and 108e are formed on the p.sup.+ -type impurity diffusion regions 113a and 113b, respectively. Gate electrode 106b, gate insulating film 105b and source/drain regions 112a, 112b, 113a and 113b form field-effect transistor 138b. A silicide protection film 109 made of a TEOS oxide film is formed on gate electrode 106b and source/drain regions 112a, 112b, 113a and 113b.
An interlayer nitride film 114, which serves as an etching stopper when forming an opening 129, is formed on field-effect transistors 138a and 138b and isolating oxide film 104. An interlayer insulating film 115 is formed on interlayer nitride film 114. In a region located above n.sup.+ -type impurity diffusion region 111a, interlayer insulating film 115 and interlayer nitride film 114 are partially removed by etching, and thereby an opening 129 is formed. A metal electrode 116 is formed in opening 129 and on interlayer insulating film 115. An interconnection 130 is formed on interlayer insulating film 115.
Referring to FIGS. 31-35, description will be given on steps of manufacturing the semiconductor device shown in FIG. 30. FIGS. 31 to 35 are schematic cross sections showing a method of manufacturing the semiconductor device shown in FIG. 30.
First, isolating oxide film 104 (see FIG. 31) is formed at the main surface of semiconductor substrate 101 (see FIG. 31) to isolate the element formation regions from each other. Then, an ion implantation method is executed to form p- and n-wells 102 and 103 at the main surface of semiconductor substrate 101. By thermally oxidizing the main surface of semiconductor substrate 101, an oxide film which will form the gate insulating film is formed on the main surface of semiconductor substrate 101. This oxide film has a film thickness of about several nanometers. A polycrystalline silicon film which will form the gate electrode is formed on this oxide film. This polycrystalline silicon film has a film thickness of about tens of nanometers. A resist pattern is formed on this polycrystalline silicon film. Using this resist pattern as a mask, etching is effected to remove portions of the polycrystalline silicon film and the insulating film so that gate insulating films 105a and 105b as well as gate electrodes 106a and 106b (see FIG. 31) are formed. Thereafter, the resist pattern is removed. An ion implanting method is executed to form n.sup.- -type impurity diffusion regions 110a and 110b as well as p.sup.- -type impurity diffusion regions 112a and 112b at the main surface of semiconductor substrate 101. Thereafter, a TEOS oxide film 117 is deposited on gate electrodes 106a and 106b, the main surface of semiconductor substrate 101 and isolating oxide film 104. TEOS oxide film 117 has a film thickness of about 60 nm. In this manner, the structure shown in FIG. 31 is obtained.
As shown in FIG. 32, etchback is effected to remove partially TEOS oxide film 117. Thereby, side walls 107a-107d are formed on the side surfaces of gate electrodes 106a and 106b, respectively. The etching for removing TEOS oxide film 117 causes over-etching of about 40%. Therefore, the upper surface portion of isolating oxide film 104 is removed by a thickness A. More specifically, TEOS oxide film 117 is removed by about 60 nm in thickness, and a portion of thickness A (which is also referred to as a "removal thickness A" or a "drop amount" hereinafter) of about 25 nm is removed from isolating oxide film 104.
As shown in FIG. 32, the ion implanting method is executed to implant n- and p-type impurities into the main surface of semiconductor substrate 101. Thereby, n.sup.+ -type impurity diffusion regions 111a and 111b as well as p.sup.+ -type impurity diffusion regions 113a and 113b are formed.
As shown in FIG. 33, a TEOS oxide film 118 is then deposited on gate electrodes 106a and 106b, the main surface of semiconductor substrate 101 and isolating oxide film 104. TEOS oxide film 118 has a film thickness of about 100 nm. A resist pattern 119 is formed on TEOS oxide film 118.
Then, as shown in FIG. 34, TEOS oxide film 118 masked with resist pattern 119 is partially removed by etching so that silicide protection film 109 made of the TEOS oxide film is formed. Thereafter, resist pattern 119 is removed.
This etching for partially removing TEOS oxide film 118 likewise causes over-etching of about 40%. This over-etching removes the upper surface portion having a film thickness B from isolating oxide film 104 as shown in FIG. 34. In this case, since TEOS oxide film 118 has a film thickness of 100 nm, and the removed portion of isolating oxide film 104 has film thickness B (which will also be referred to as a "removal thickness" or a "drop amount" hereinafter) of about 40 nm.
A high-melting-point metal film is formed on gate electrode 106a, the main surface of semiconductor substrate 101, isolating oxide film 104 and silicide protection film 109 by a sputtering method. Lamp annealing is executed as thermal treatment. As a result, a silicide reaction occurs at the main surface of semiconductor substrate 101 and the upper surface of gate electrode 106a, and particularly at contact portions where silicon and polycrystalline silicon are in contact with the high-melting-point metal film. Consequently, high-melting-point metal silicide layers 108a-108e (see FIG. 35) are formed. Thereafter, the unreacted high-melting-point metal layer is removed so that the structure shown in FIG. 35 is formed.
After the above steps, interlayer nitride film 114 is deposited on the entire surface of semiconductor substrate 101. Further, interlayer insulating film 115 is deposited on interlayer nitride film 114. The upper surface of interlayer insulating film 115 is flattened by a CMP (Chemical Mechanical Polishing) method. A resist pattern is formed on interlayer insulating film 115. Using this resist pattern as a mask, interlayer insulating film 115 and interlayer nitride film 114 are partially removed to form opening 129. In this etching process for forming opening 129, etching conditions providing a high selectivity of interlayer insulating film 115 to nitride film 114 ((an etch rate of interlayer insulating film 115)/(an etch rate of nitride film 114)) are first employed for removing interlayer insulating film 115 and stopping the progress of etching in interlayer nitride film 114. Thereafter, interlayer nitride film 114 is etched under different etching conditions. Then, metal electrode 116 and interconnection 130 are formed. In this manner, the semiconductor device shown in FIG. 30 is obtained.
However, the conventional semiconductor device described above suffers from the problems, which will now be described with reference to FIGS. 36 and 37.
FIG. 36 is a schematic fragmentary cross section showing, on an enlarged scale, an ideal semiconductor device. FIG. 37 is a schematic fragmentary cross section showing, on an enlarged scale, the semiconductor device, and particularly shows objects to be achieved by the invention.
Referring to FIG. 36, a field-effect transistor 138a is formed on the main surface of semiconductor substrate 101. It is preferable that isolating oxide film 104 neighboring to n.sup.+ -type impurity diffusion regions 111a and 111b of field-effect transistor 138a has the upper surface located at the substantially same level as the main surface of semiconductor substrate 101. In this case, p-well 102 can be kept at a potential different from that of n.sup.+ -type impurity diffusion regions 111a and 111b. For example, +2 V may be placed on n.sup.+ -type impurity diffusion regions 111a and 111b, and .+-.0 V may be placed on p-well 102, in which case a reverse bias occurs so that only a little current of tens of fA/.mu.m.sup.2 occurs.
In the conventional semiconductor device shown in FIG. 30, the upper surface of isolating oxide film 104 is located at a lower level than the main surface of semiconductor substrate 101 as shown in FIG. 37. This is because the upper surface of isolating oxide film 104 is over-etched in the etching process, which is executed for forming side walls 107a-107d and silicide protection films 109. The drop amount of the upper surface of isolating oxide film 104 (i.e., a sum of thickness A of the portion removed by the over-etching in the etching process for forming side walls 107a-107d and thickness B of the portion removed by the over-etching in the etching process for forming silicide protection film 109) is larger than a depth Xj of n.sup.+ -type impurity diffusion regions 111a and 111b. In this case, as can be seen in regions 100, each of high-melting-point metal silicide layers 108a and 108c is formed over not only n.sup.+ -type impurity diffusion region 111a (or 111b) but also p-well 102. Therefore, n.sup.+ -type impurity diffusion regions 111a and 111b are short-circuited to p-well 102 via high-melting-point metal silicide layers 108a and 108c, respectively. Consequently, such a disadvantage occurs that n.sup.+ -type impurity diffusion regions 111a and 111b carry the same potential as p-well 102, or that a large leak current flows even when n.sup.+ -type impurity diffusion regions 111a and 111b carry the potential different from that of p-well 102. For example, when n.sup.+ -type impurity diffusion regions carry +2 V and p-well 102 carries .+-.0 V, a reverse bias occurs at the junction boundary surface between the above region and the well, but a large leak current (of hundreds of femtoamperes or more) occurs via high-melting-point metal silicide layers 108a and 108c. The above problem likewise occurs between n-well 103 and p.sup.+ -type impurity diffusion regions 113a and 113b in field-effect transistor 138b.
When the large leak current flows as described above, the semiconductor device malfunctions, and reliability of the semiconductor device is remarkably reduced.